Advanced Semiconductor Fabrication

Bardeen's IGFET concept forms the conceptual basis of modern MOSFET technology. It predated practical silicon MOS fabrication by more than a decade.

While working at Bell Telephone Laboratories, Frosch and Derick grew an oxide layer over a silicon wafer and observed that it passivated the surface. Surface passivation by thermal oxide became a foundation of all subsequent silicon device fabrication.

By 1957 the pair could manufacture silicon dioxide transistors in which drain and source were adjacent at the same surface. Bell Labs immediately recognised the importance, circulating memos internally before formal publication, and the preprint reached Shockley Semiconductor's senior staff in December 1956.

Hoerni, who had received the Frosch and Derick preprint while at Shockley Semiconductor, devised the planar process at Fairchild. It became the standard method for building integrated circuits on a wafer surface.

Device manufacturing originated in concentrated clusters in Texas and California during the 1960s. From there the capability diffused worldwide, laying the basis for today's globally distributed industry.

Wafers grew from 25 mm in 1960 to 50 mm in 1969, 100 mm in 1976, 125 mm in 1981, 150 mm in 1983 and 200 mm in 1992. Each increase raised usable surface area per wafer and forced changes in handling, from manual tweezers to cassettes and then robotics.

Contamination control in the 1960s was loose enough that street clothes were acceptable in production areas. Later cleanroom discipline, mini-environments and FOUPs reflect how defect sensitivity rose with shrinking feature sizes.

CMOS was an improved form of MOSFET technology combining complementary devices for very low standby power. It became the dominant process technology for integrated circuits.

Manasevit documented silicon-on-sapphire epitaxy and published the findings with William Simpson in the Journal of Applied Physics in 1964. The technique opened a route to insulating-substrate devices.

The pair demonstrated that MOS devices could be built on the sapphire substrate pioneered by Manasevit. This established silicon-on-insulator fabrication as a practical variant.

RCA began commercial CMOS production starting with a 20 μm process, gradually scaling to 10 μm over the following years. Many early manufacturers of the era also built their own fabrication equipment, such as ion implanters.

Several companies shifted their semiconductor manufacturing base from bipolar processes to MOS over these two decades. The transition set the technological direction for subsequent scaling.

Doping was initially done by thermal diffusion in furnaces at 900 to 1200 °C, and ion implantation faced resistance because it still required a separate furnace. Implantation prevailed because it offered far better reproducibility, though diffusion survives in silicon photovoltaic manufacture.

Wet etching was widely used in the 1960s and 1970s before being displaced by dry plasma etching at the 10 micron to 3 micron nodes. Plasma etching allowed the anisotropic profiles needed for further miniaturisation.

In the 1970s wires attaching die to package were attached by hand. Automated bonding machines now perform the task, part of the broader automation of back-end assembly.

Semiconductor manufacturing equipment has been considered expensive since 1978. Rising tool costs became a structural barrier to entry at successive nodes.

PVD was the primary means of depositing materials onto wafers until CVD arrived. Around the same time diffusion pumps gave way to oil-free turbomolecular pumps, reducing wafer contamination in vacuum processing.

Automated mask inspection replaced error-prone manual checking of the patterns used in photolithography. It was followed in 1985 by KLA's automatic silicon wafer inspection tool, which replaced manual microscope inspection.

BCD, also called BCDMOS, integrated three device types in one manufacturing flow. It remains widely used for power and analogue products, many still built on 200 mm wafers.

The Precision 5000 grouped several process chambers around a shared handling platform. Cluster architecture became the standard configuration for advanced deposition and etch equipment.

200 mm diameter wafers were first used in 1990 and became the standard until 300 mm wafers were introduced in 2000. Bridge tools eased each transition, and the 300 mm era brought the adoption of FOUP wafer carriers.

IBM announced the world's first technology able to produce chips smaller than one nanometre. It extended the frontier of advanced node fabrication beyond the nanometre threshold.

The Chinese team announced a working 32-bit RISC-V processor built using two-dimensional semiconductor materials at the 1 nm scale. It demonstrated a potential route past silicon at the extreme limit of scaling.

Washington pressed the Taiwanese foundry to stop fabricating chips for the Chinese firm. The move marked the use of advanced fabrication access as an instrument of state power.

The COVID-19 pandemic triggered a multi-year shortage during which manufacturers confined employees to company grounds and counterfeit chips proliferated. Many countries responded by granting subsidies for new fabrication plants, as semiconductors became vital to national economies and security.

TSMC reported an average yield of about 80 per cent with peak per-wafer yield above 90 per cent for 5 nm test chips of 17.92 mm2. Yield fell to 32 per cent when die size rose to 100 mm2, illustrating the yield sensitivity that defines leading-edge mastery.

As of 2019, 14 nm and 10 nm were in mass production at Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory and GlobalFoundries, with 7 nm in mass production only at TSMC and Samsung. Samsung began 5 nm production in 2018, TSMC's 5 nm N5 reached 171.3 million transistors per square millimetre, and both firms announced 3 nm nodes in 2019.

The company judged that building a fab for sub-12 nm orders was beyond its financial abilities and halted new node development to save resources. Its exit further narrowed the set of firms able to fabricate at the leading edge.

By 2018 numerous proposals existed based on gate-all-around concepts: horizontal and vertical nanowires, nanosheet transistors such as Samsung MBCFET and Intel Nanoribbon, vertical FETs, complementary and stacked FETs, III-V FinFETs and negative-capacitance FETs. FD-SOI was seen as a potential low-cost alternative to FinFET.

Copper interconnects would be encapsulated in cobalt to prevent electromigration, replacing tantalum nitride which must be thicker in this role. Electromigration had become increasingly evident from the 16 nm node onward.

The fin geometry wraps the gate around the channel on three sides, improving energy efficiency and gate delay where planar transistors suffered short-channel effects. A startup, SuVolta, offered a competing lightly doped planar approach called Deeply Depleted Channel at 65 nm.

Since 2009 the node label has indicated a generation of process technology with no relation to gate length, metal or gate pitch; the trend of gate length being smaller than the node name also reversed that year. GlobalFoundries' 7 nm was comparable to Intel's 10 nm, and TSMC and Samsung's 10 nm processes sit closer to Intel's 14 nm in density.

HKMG replaced polysilicon gates, which had themselves replaced aluminium metal gates in the 1970s. The same technology was first adopted in DRAM memories in 2015.

In 2006 the next wafer-size steps were expected to arrive within a decade. The forecast did not materialise, and 300 mm has remained the largest production wafer size.

During the 200 mm to 300 mm wafer transition of 2001, eighteen firms could manufacture chips at the leading-edge 130 nm node. The number has since collapsed as node costs rose, a key marker of consolidation in advanced fabrication.

SOI technology underpinned AMD's single, dual, quad, six and eight core processors made from 2001 onward at 130, 90, 65, 45 and 32 nm. It represented an alternative scaling path to bulk silicon.

The Producer grouped chambers in pairs sharing vacuum and supply lines while remaining otherwise isolated. It was revolutionary for offering higher productivity than other cluster tools without sacrificing process quality.

IBM replaced aluminium wiring with lower-resistance copper in chip interconnects. Copper wiring is standard in modern semiconductors and drives the nitrogen-purged FOUP environments used to prevent oxidation.

BEoL has been used since 1995 at the 350 nm and 250 nm nodes, with CMP introduced at the same time. Planarisation by CMP made multi-level metal interconnect stacks feasible.

From 1994 the nanometre figures used to name process nodes ceased to correspond to functional feature sizes or transistor density. The node name became a marketing term, complicating comparisons between manufacturers.

Historically yield loss was mainly caused by dust particles, but since the 1990s it is mainly attributable to process variation, the process itself and the tools used. Dust nonetheless remains a problem in many older fabs.